11月4日下午2:00曹楼231会议室，进行普迪飞半导体技术（上海）有限公司招聘宣讲，第二天进行面试。
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具体招聘岗位如下：
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1、数据分析工程师第 1 级（Level 1）
主要目的：为客户顾问小组提供准确，全面和及时的标准数据分析以解决良率及技术问题。推动公司在数据分析和方法论专长领域的进一步发展。
特殊要求：需出差美国和其它国家 PDF Solutions 分支机构（培训，公司会议等）
职位要求:
学历：微电子、电子工程、材料科学 、物理或相关领域的学士，硕士或博士。
语言：通过大学英语四、六级考试。口语及书面英语能满足沟通工作交流及解决技术问题的要求。能以英语撰写报告、文件和电子邮件。能有效地用英语面对面或用电话沟通，流利者更佳。
经验：不需经验，但有半导体产品或工艺数据分析经验者优先考虑。
2、设计工程师CV Test Chip Designer (DFT)
Job description:
- Design, generate and verify specific Characterization Vehicle® test chip layouts to characterize clients’ manufacturing processes and quantify impact of design on product performance and yield. Focus on short flow (BEOL, FEOL) test chips.
- Use PDF proprietary automated layout tools including layout generators, routers and packers to create, place and route CV test chip structures.
- Generate all collateral needed for testing, inspection, analysis, and documentation of CV® Test Chips.
- Participate with client in detailed review of test chip including post-OPC data review and pre mask-making reviews
- Work closely with PDF CV Analysis Methods to create an optimal design of experiments for CV® test chips.
工作内容：
- 设计、实现、验证CV(Characterization Vehicle®) 测试芯片的版图, 以用于诊断客户生产制程和量化分析设计对于产品性能及良率的影响。前端和后端均在其内。
- 使用PDF专有的自动化版图设计工具（包括版图生成器，布局布线工具等）设计实现测试芯片。
- 提取版图参数及其它所需，用于CV芯片的测试，检查，分析，和存档。
- 与客户合作参与测试芯片的详细检查，包括OPC之后和掩模版制造前的数据检查。
- 与 PDF CV分析领域紧密合作，给出测试芯片的最佳实验设计方案。
Required skills and experience:
- Sound understanding of semiconductor manufacturing process and transistors
- Experience with semiconductor layout methods and layout tool suites (e.g., Cadence,
- Working knowledge of DRC and LVS tools and deck creation and applicatoin
- Basic knowledge of Unix scripting languages (e.g., perl, CSH, SH, Tcl, etc)
- Basic knowledge of parametric test methods
- Self-motivated and highly professional including some experience with customer interactions
- Familiarity with interpreting and using Design Rule Manuals for deep sub-micron semiconductor processes (both foundry and IDM)
品格/能力/经验要求：
- 理解半导体制造工艺和晶体管结构。
- 版图设计和相关设计工具（如Cadence, Mentor等）使用经验。
- DRC和LVS相关知识和经验。
- Unix脚本语言的基础知识（如perl, CSH, SH, Tcl等）
- 参数测试方法的基础知识。
- 自动自发，敬业，专业；如有与客户沟通经验更佳。
- 熟练地理解并使用深亚微米半导体工艺的设计规则手册。
Job desirables:
- Experience with Cadence Virtuoso and/or Cadence SKILL programming language
- Experience with
- Experience with any part of Design for Manufacturability including design modification, verification, algorithms or failure analysis
- Experience using circuit modeling software (HSPICE, Spectre, etc)
- Familiarity with semiconductor reticle-making practices (mask data prep, dummy fill algorithms, basics of OPC, mask fracturing and biasing, etc)
如有更佳：
- Cadence Virtuoso / Cadence Skill语言编程经验
- Mentor Graphic Calibre DRC使用经验
- 任何DFM有关的经验，包括设计修改、验证、算法设计或者失效分析
- 实验设计有关的经验
- 电路仿真软件使用经验（HSPICE, Spectre等）
- 熟悉半导体生产实例（如掩模数据准备，dummy fill算法， OPC基础知识，掩模板其他相关经验等）。
3、Application Engineer
Job Description:
1. Work with PDF teams across the world on generating key components of PDF CV infrastructure.
2. Define test structure measure plan for PDF tester.
3. Deliver users reference document for analysis team on how to analyze test structures.
4. Deliver test chip config for test date integrated into database.
What you can get:
- Systematic entrance training and follow up on-job training.
- Good understanding of PDF methodology and work flow from various aspects.
- More opportunity to exercise your customer services skills, both internally and externally.
- Improve problem solving skill significantly.
- Work with talented PDF people across the world.
Our target:
- Candidate with Electrical Engineering or Computer Science background, or related major.
- Familiar with Linux, Shell, Perl is a plus.
- Good at both writing and oral English.
- Full of passion and good customer services attitude.
- Responsible and detail oriented.
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